

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity I2CmasterDemoTestbench is
end I2CmasterDemoTestbench;

architecture test of I2CmasterDemoTestbench is

  component I2CmasterDemo_synth is
    port (
    I2C_Data : inout STD_LOGIC; 
    I2C_Clk : out STD_LOGIC; 
    SW : in STD_LOGIC; 
    FPGA_Clk : in STD_LOGIC := 'X' 
  );
  end component;
  
  component I2CmasterDemo_par is
  port (
    I2C_Data : inout STD_LOGIC; 
    I2C_Clk : out STD_LOGIC; 
    FPGA_Clk : in STD_LOGIC := 'X'; 
    SW : in STD_LOGIC_VECTOR ( 3 downto 0 ) 
  );
  end component;

  component I2CmasterDemo is
    Port ( FPGA_Clk : IN std_logic;
		       I2C_Clk : out std_logic;
    		     I2C_Data : inout std_logic;
    	   	  SW : IN std_logic);
  end component;
  
  signal sFPGA_Clk,sI2C_Clk,sClk : std_logic:='0';
  signal sI2C_Data : std_logic:='1';
  signal sSW : std_logic_vector(3 downto 0):="0000";

begin
  
  UUT: I2CmasterDemo port map(sFPGA_Clk,sI2C_Clk,sI2C_Data,sSW(3));
  --UUT: I2CmasterDemo_par port map(sI2C_Data,sI2C_Clk,sFPGA_Clk,sSW);
  
  sFPGA_Clk<= not sFPGA_Clk after 20 ns;
  
  process
  begin
    report("wait for bootup 100ns");
    wait for 10 us;
    
    report("pulsing switch, ends on 100us");
    sSW(3)<='1';
    wait for 200 ms;
    sSW(3)<='0';
    report("switch off");
    
    wait;
  end process;
end test;